Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
11.2 SIOP Signal Format
The SIOP subsystem is software configurable for master or slave operation. No
8
2
external mode selection inputs are available (such as the slave select pin).
11.2.1 Serial Clock (SCK)
3
The state of the SCK output normally remains a logic one during idle periods
between data transfers. The first falling edge of SCK signals the beginning of a
data transfer. At this time the first bit of received data is accepted at the SDI pin
and the first bit of transmitted data is presented at the SDO pin (see Figure 11-2).
Data is captured at the SDI pin on the rising edge of SCK, and the first bit of
transmitted data is presented at the SDO pin. The transfer is terminated upon the
eighth rising edge of SCK.
4
5
6
7
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
SDO
SCK
SDI
8
9
100 ns
100 ns
10
11
12
13
14
A
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
Figure 11-2. SIOP Timing Diagram
The master and slave modes of operation differ only by the sourcing of SCK. In
master mode, SCK is driven from an internal source within the MCU. In slave
mode, SCK is driven from a source external to the MCU. The SCK frequency is
programmable via the mask option register 1 (MOR1). Available rates are OSC
divided by 2, 4, 8, or 16.
NOTE
16
17
18
19
20
OSC divided by 2 is four times faster than the standard rate available
on the 68HC05P6.
Refer to 8.4 Mask Option Registers (MOR) for a description of available mask
option registers.
SERIAL INPUT/OUTPUT PORT
MC68HC805P18
11-2
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
