Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
11.3.3 SIOP Data Register (SDR)
8
2
This register is located at address $000C and serves as both the transmit and
receive data register. Writing to this register will initiate a message transmission if
the SIOP is in master mode. The SIOP subsystem is not double buffered and any
write to this register will destroy the previous contents. The SDR can be read at any
time; however, if a transfer is in progress, the results may be ambiguous and the
DCOL bit will be set. Writing to the SDR while a transfer is in progress can cause
invalid data to be transmitted and/or received. Figure 11-3 shows the position of
each bit in the register. This register is not affected by reset.
3
4
5
Bit 7
SD7
6
5
4
3
2
1
Bit 0
SD0
6
Read:
Write:
Reset:
SDR
$000C
SD6
SD5
SD4
SD3
SD2
SD1
7
Unaffected by reset
Figure 11-5. SIOP Data Register
8
9
10
11
12
13
14
A
16
17
18
19
20
SERIAL INPUT/OUTPUT PORT
MC68HC805P18
11-6
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