Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
10.6 Timer Status Register (TSR)
8
2
Reading the timer status register (TSR) satisfies the first condition required to clear
status flags and interrupts. See Figure 10-3. The only remaining step is to read (or
write) the register associated with the active status flag (and/or interrupt). This
method does not present any problems for input capture or output compare
functions.
3
However, a problem can occur when using a timer interrupt function and reading
the free-running counter at random times to, for example, measure an elapsed
time. If the proper precautions are not designed into the application software, a
timer interrupt flag (TOF) could unintentionally be cleared if:
4
5
1. The TSR is read when bit 5 (TOF) is set, and
6
2. The LSB of the free-running counter is read, but not for the purpose of
servicing the flag or interrupt.
7
The alternate counter registers (ACRH and ACRL) contain the same values as the
timer registers (TMRH and TMRL). Registers ACRH and ACRL can be read at any
time without affecting the timer overflow flag (TOF) or interrupt.
8
9
Bit 7
ICF
6
5
4
0
3
0
2
0
1
0
Bit 0
0
10
11
12
13
14
A
Read:
Write:
Reset:
OCR
TOF
TSR
$0013
X
X
X
0
0
0
0
0
= Unimplemented
Figure 10-11. Timer Status Register (TSR)
ICF — Input Capture Flag
Bit 7 is set when the edge specified by IEDG in register TCR has been sensed
by the input capture edge detector fed by pin TCAP. This flag and the input
capture interrupt can be cleared by reading register TSR followed by reading the
LSB of the input capture register pair (ICRL).
16
17
18
19
20
OCF — Output Compare Flag
Bit 6 is set when the contents of the output compare registers match the
contents of the free-running counter. This flag and the output compare interrupt
can be cleared by reading register TSR followed by writing the LSB of the output
compare register pair (OCRL).
16-BIT TIMER
Rev. 1.0
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