Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
11.3.1 SIOP Control Register (SCR)
8
2
This register is located at address $000A and contains two bits. Figure 11-3 shows
the position of each bit in the register and indicates the value of each bit after reset.
Bit 7
0
6
SPE
0
5
0
4
MSTR
0
3
0
2
0
1
0
Bit 0
0
3
Read:
Write:
Reset:
SCR
$000A
4
0
0
0
0
0
0
5
= Unimplemented
Figure 11-3. SIOP Control Register
6
7
SPE — Serial Peripheral Enable
When set, the SPE bit enables the SIOP subsystem such that SDO/PB5 is the
serial data output, SDI/PB6 is the serial data input, and SCK/PB7 is a serial
clock input in the slave mode or a serial clock output in the master mode. Port
B DDR and data registers can be manipulated as usual (except for PB5);
however, these actions could affect the transmitted or received data.
8
9
10
11
12
13
14
A
The SPE bit is readable and writable at any time. Clearing the SPE bit while a
transmission is in progress will 1) abort the transmission, 2) reset the serial bit
counter, and 3) convert the port B/SIOP port to a general-purpose I/O port.
Reset clears the SPE bit.
MSTR — Master Mode Select
When set, the MSTR bit configures the serial I/O port for master mode. A
transfer is initiated by writing to the SDR. Also, the SCK pin becomes an output
providing a synchronous data clock dependent upon the oscillator frequency.
When the device is in slave mode, the SDO and SDI pins do not change
function. These pins behave exactly the same in both the master and slave
modes.
The MSTR bit is readable and writable at any time regardless of the state of the
SPE bit. Clearing the MSTR bit will abort any transfers that may have been in
progress. Reset clears the MSTR bit, placing the SIOP subsystem in slave
mode.
16
17
18
19
20
SERIAL INPUT/OUTPUT PORT
MC68HC805P18
11-4
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