Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
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SECTION 11
SERIAL INPUT/OUTPUT PORT
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11.1 Introduction
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The simple synchronous serial input/output port (SIOP) subsystem is designed to
provide efficient serial communications between peripheral devices or other
MCUs. The SIOP is implemented as a 3-wire master/slave system with serial clock
(SCK), serial data Input (SDI), and serial data output (SDO). A block diagram of the
SIOP is shown in Figure 11-1.
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The SIOP subsystem shares its input/output pins with port B. When the SIOP is
enabled (SPE bit set in register SCR), port B data direction registers (DDR) and
data registers are modified by the SIOP. Although port B DDR and data registers
can be altered by application software, these actions could affect the transmitted
or received data.
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A
HCO5 INTERNAL BUS
SPE
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
BAUD
SDO/PB5
SDI/PB6
8-BIT
SDO
SDI
I/O
STATUS
CONTROL
REGISTER
RATE
SHIFT
REGISTER
$0C
CONTROL
LOGIC
REGISTER
$0B
GENERATOR
$0A
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SCK
SCK/PB7
PH2 CLOCK
Figure 11-1. SIOP Block Diagram
SERIAL INPUT/OUTPUT PORT
Rev. 1.0
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