Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
11.3.2 SIOP Status Register (SSR)
8
2
This register is located at address $000B and contains two bits. Figure 11-3 shows
the position of each bit in the register and indicates the value of each bit after reset.
Bit 7
6
5
0
4
0
3
0
2
0
1
0
Bit 0
0
3
Read:
Write:
Reset:
SPIF
DCOL
SSR
$000B
4
0
0
0
0
0
0
0
0
5
= Unimplemented
Figure 11-4. SIOP Status Register
6
SPIF — Serial Port Interface Flag
7
SPIF is a read-only status bit that is set on the last rising edge of SCK and
indicates that a data transfer has been completed. It has no effect on any future
data transfers and can be ignored. The SPIF bit is cleared by reading the SSR
followed by a read or write of the SDR. If the SPIF is cleared before the last rising
edge of SCK, it will be set again on the last rising edge of SCK. Reset clears the
SPIF bit.
8
9
10
11
12
13
14
A
DCOL — Data Collision
DCOL is a read-only status bit which indicates that an illegal access of the SDR
has occurred. The DCOL bit will be set when reading or writing the SDR after
the first falling edge of SCK and before SPIF is set. Reading or writing the SDR
during this time will result in invalid data being transmitted or received.
The DCOL bit is cleared by reading the SSR (when the SPIF bit is set) followed
by a read or write of the SDR. If the last part of the clearing sequence is done
after another transfer has started, the DCOL bit will be set again. Reset clears
the DCOL bit.
16
17
18
19
20
SERIAL INPUT/OUTPUT PORT
Rev. 1.0
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