Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
TOF — Timer Overflow Flag
8
2
Bit 5 is set by a rollover of the free-running counter from $FFFF to $0000. This
flag and the timer overflow interrupt can be cleared by reading register TSR
followed by reading the LSB of the timer register pair (TMRL).
3
10.7 Timer Operation During Wait/Halt Modes
During wait and halt modes, the 16-bit timer continues to operate normally and may
generate an interrupt to trigger the MCU out of the wait/halt mode.
4
5
10.8 Timer Operation During Stop Mode
6
When the MCU enters the stop mode, the free-running counter stops counting (the
PH2 clock is stopped). It remains at that particular count value until the stop mode
is exited by applying a low signal to the IRQ pin, at which time the counter resumes
from its stopped value as if nothing had happened. If stop mode is exited via an
external RESET (logic low applied to the RESET pin), the counter is forced to
$FFFC.
7
8
9
If a valid input capture edge occurs at the TCAP pin during stop mode the input
capture detect circuitry will be armed. This action does not set any flags or “wake
up” the MCU, but when the MCU does “wake up” there will be an active input
capture flag (and data) from the first valid edge. If the stop mode is exited by an
external RESET, no input capture flag or data will be present even if a valid input
capture edge was detected during stop mode.
10
11
12
13
14
A
16
17
18
19
20
16-BIT TIMER
MC68HC805P18
10-12
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