Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
10.5 Timer Control Register (TCR)
8
2
The timer control (TCR) shown in Figure 10-3 and free-running counter (TMRH,
TMRL, ACRH, and ACRL) registers are the only registers of the 16-bit timer
affected by reset. The output compare port (TCMP) is forced low after reset and
remains low until OLVL is set and a valid output compare occurs.
3
Bit 7
ICIE
0
6
OCIE
0
5
TOIE
0
4
0
3
0
2
0
1
IEDG
X
Bit 0
OLVL
0
4
Read:
Write:
Reset:
TCR
$0012
5
0
0
0
6
= Unimplemented
Figure 10-10. Timer Control Register (TCR)
7
ICIE — Input Capture Interrupt Enable
8
Bit 7, when set, enables input capture interrupts to the CPU. The interrupt will
occur at the same time bit 7 (ICF) in the TSR register is set.
9
OCIE —Output Compare Interrupt Enable
10
11
12
13
14
A
Bit 6, when set, enables output compare interrupts to the CPU. The interrupt will
occur at the same time bit 6 (OCF) in the TSR register is set.
TOIE — Timer Overflow Interrupt Enable
Bit 5, when set, enables timer overflow (rollover) interrupts to the CPU. The
interrupt will occur at the same time bit 5 (TOF) in the TSR register is set.
IEDG — Input Capture Edge Select
Bit 1 selects which edge of the input capture signal will trigger a transfer of the
contents of the free-running counter registers to the input capture registers.
Clearing this bit will select the falling edge; setting it selects the rising edge.
OLVL — Output Compare Output Level Select
16
17
18
19
20
Bit 0 selects the output level (high or low) that is clocked into the output compare
output latch at the next successful output compare.
16-BIT TIMER
MC68HC805P18
10-10
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