Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
After a read of the MSB of the input capture register pair (ICRH), counter transfers
are inhibited until the LSB of the register pair (ICRL) is also read. This characteristic
forces the minimum pulse period attainable to be determined by the time required
to execute an input capture software routine in an application.
8
2
Reading the LSB of the input capture register pair (ICRL) does not inhibit transfer
of the free-running counter. Again, minimum pulse periods are ones which allow
software to read the LSB of the register pair (ICRL) and perform needed
operations. There is no conflict between reading the LSB (ICRL) and the
free-running counter transfer, since they occur on opposite edges of the PH2 clock.
3
4
5
6
PH2
CLOCK
7
16-BIT
FREE-RUNNING
COUNTER
$FFEB
$FFEC
$FFED
$FFEE
$FFEF
8
TCAP
PIN
9
(SEE NOTE)
INPUT
CAPTURE
LATCH
10
11
12
13
14
A
INPUT
CAPTURE
REGISTER
$????
$FFED
INPUT
CAPTURE
FLAG
NOTE: If the input edge occurs in the shaded area from one T10 timer state to the other T10 timer state, the input capture
flag is set during the next T11 timer state.
Figure 10-9. State Timing Diagram for Input Capture
16
17
18
19
20
16-BIT TIMER
Rev. 1.0
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
