Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
10.4 Input Capture
Two 8-bit read-only registers (ICRH and ICRL) make up the 16-bit input capture.
8
2
They are used to latch the value of the free-running counter after a defined
transition is sensed by the input capture edge detector.
3
NOTE
4
The input capture edge detector contains a Schmitt trigger to improve
noise immunity.
5
6
The edge that triggers the counter transfer is defined by the input edge bit (IEDG)
in register TCR. Reset does not affect the contents of the input capture registers.
See Figure 10-3.
7
8
Bit 7
ICRH7
X
6
ICRH6
X
5
ICRH5
X
4
ICRH4
X
3
ICRH3
X
2
ICRH2
X
1
ICRH1
X
Bit 0
ICRH0
X
9
Read:
Write:
Reset:
ICRH
$0014
10
11
12
13
14
A
Bit 7
ICRL7
X
6
ICRL6
X
5
ICRL5
X
4
ICRL4
X
3
ICRL3
X
2
ICRL2
X
1
ICRL1
X
Bit 0
ICRL0
X
Read:
Write:
Reset:
ICRL
$0015
Figure 10-8. Input Compare Registers (ICRH/ICRL)
The result obtained by an input capture will be one more than the value of the
free-running counter on the rising edge of the PH2 clock preceding the external
transition (see Figure 10-9). This delay is required for internal synchronization.
Resolution is affected by the prescaler, allowing the free-running counter to
increment once every four PH2 clock cycles.
16
17
18
19
20
The contents of the free-running counter are transferred to the input capture
registers on each proper signal transition regardless of the state of the input
capture flag bit (ICF) in register TSR. The input capture registers always contain
the free-running counter value which corresponds to the most recent input capture.
16-BIT TIMER
MC68HC805P18
10-8
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