Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
Since neither the output compare flag (OCF) nor the output compare registers are
affected by reset, care must be exercised when initializing the output compare
function. The following procedure is recommended:
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1. Block interrupts by setting the I bit in the condition code register (CCR).
2. Write the MSB of the output compare register pair (OCRH) to inhibit further
compares until the LSB is written.
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3. Read the timer status register (TSR) to arm the output compare flag (OCF).
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4. Write the LSB of the output compare register pair (OCRL) to enable the
output compare function and to clear its flag (and interrupt).
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5. Unblock interrupts by clearing the I bit in the CCR.
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This procedure prevents the output compare flag bit (OCF) from being set between
the time it is read and the time the output compare registers are updated. A
software example is shown in Figure 10-7.
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SEI
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9B
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BLOCK INTERRUPTS
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.
.
9
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.
.
.
XX
XX
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13
17
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LDA
LDX
STA
LDA
STX
.
B6
BE
B7
B6
BF
.
DATAH
DATAL
OCRH
TSR
OCRL
.
HI BYTE FOR COMPARE
LO BYTE FOR COMPARE
INHIBIT OUTPUT COMPARE
ARM OCF BIT TO CLEAR
READY FOR NEXT COMPARE
.
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14
A
Figure 10-7. Output Compare Software Initialization Example
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16-BIT TIMER
Rev. 1.0
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