Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
10.3 Output Compare
The output compare function may be used to generate an output waveform and/or
8
2
as an elapsed time indicator. All of the bits in the output compare register pair
OCRH/OCRL are readable and writable and are not altered by the 16-bit timer’s
control logic. Reset does not affect the contents of these registers. If the output
compare function is not utilized, its registers can be used for data storage. See
Figure 10-3.
3
4
Bit 7
6
5
4
3
2
1
Bit 0
5
Read:
Write:
Reset:
OCRH
$0016
OCRH7 OCRH6 OCRH5 OCRH4 OCRH3 OCRH2 OCRH1 OCRH0
6
X
X
6
X
5
X
4
X
3
X
2
X
1
X
7
Bit 7
Bit 0
8
Read:
Write:
Reset:
OCRL
$0017
OCRL7 OCRL6 OCRL5 OCRL4 OCRL3 OCRL2 OCRL1 OCRL0
9
X
X
X
X
X
X
X
X
Figure 10-6. Output Compare Registers (OCRH/OCRL)
10
11
12
13
14
A
The contents of the output compare registers are compared with the contents of
the free-running counter once every four PH2 clock cycles. If a match is found, the
output compare flag bit (OCF) is set and the output level bit (OLVL) is clocked to
the output latch. The values in the output compare registers and output level bit
should be changed after each successful comparison to control an output
waveform or to establish a new elapsed timeout. An interrupt can also accompany
a successful output compare if the output compare interrupt enable bit (OCIE) is
set.
After a CPU write cycle to the MSB of the output compare register pair (OCRH),
the output compare function is inhibited until the LSB (OCRL) is written. Both bytes
must be written if the MSB is written. A write made only to the LSB will not inhibit
the compare function. The free-running counter increments every four PH2 clock
cycles. The minimum time required to update the output compare registers is a
function of software rather than hardware.
16
17
18
19
20
The output compare output level bit (OLVL) will be clocked to its output latch
regardless of the state of the output compare flag bit (OCF). A valid output compare
must occur before the OLVL bit is clocked to its output latch (TCMP).
16-BIT TIMER
MC68HC805P18
10-6
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