Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
The free-running counter is initialized to $FFFC during reset and is a read-only
register. During power-on-reset (POR), the counter is initialized to $FFFC and
begins counting after the oscillator startup delay. Because the counter is 16 bits
preceded by a fixed divide-by-four prescaler, the value in the counter repeats every
262,144 PH2 clock cycles (524,288 oscillator cycles). When the free-running
counter rolls over from $FFFF to $0000, the timer overflow flag bit (TOF) in register
TSR is set. An interrupt can also be enabled when counter rollover occurs by
setting the timer overflow interrupt enable bit (TOIE) in register TCR. See
Figure 10-5.
8
2
3
4
5
PH2
CLOCK
6
INTERNAL
RESET
7
16-BIT
FREE-RUNNING
COUNTER
$FFFC
$FFFD
$FFFE
$FFFF
8
RESET
(EXTERNAL
OR OTHER)
9
NOTE: The counter and control registers are the only 16-bit timer registers affected by reset.
10
11
12
13
14
A
Figure 10-5. State Timing Diagram for Timer Reset
16
17
18
19
20
16-BIT TIMER
Rev. 1.0
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
