Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
Bit 7
6
5
1
4
1
3
1
2
1
1
1
Bit 0
8
2
Read:
Write:
Reset:
ACRH7 ACRH6 ACRH5 ACRH4 ACRH3 ACRH2 ACRH1 ACRH0
ACRH
$001A
1
1
1
3
Bit 7
6
5
4
3
2
1
Bit 0
4
Read:
Write:
Reset:
ACRL7
ACRL6
ACRL5
ACRL4
ACRL3
ACRL2
ACRL1
ACRL0
ACRL
$001B
5
1
1
1
1
1
1
0
0
6
= Unimplemented
Figure 10-3. Alternate Counter Registers (ACRH/ACRL)
7
The timer registers and alternate counter registers can be read at any time without
affecting their value. However, the alternate counter registers differ from the timer
registers in one respect: Aread of the timer register MSB can clear the timer
overflow flag (TOF). Therefore, the alternate counter registers can be read at any
time without the possibility of missing timer overflow interrupts due to clearing of
the TOF. See Figure 10-4.
8
9
10
11
12
13
14
A
PH2
CLOCK
16-BIT
FREE-RUNNING
COUNTER
$FFFE
$FFFF
$0000
$0001
$0002
TIMER
OVERFLOW
FLAG (TOF)
NOTE: The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by reading the timer status
register (TSR) during the high portion of the PH2 clock followed by reading the LSB of the counter register pair (TCRL).
Figure 10-4. State Timing Diagram for Timer Overflow
16
17
18
19
20
16-BIT TIMER
MC68HC805P18
10-4
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
