Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
10.2 Timer
8
2
The key element of the programmable timer is a 16-bit free-running counter, or
timer registers, preceded by a prescaler which divides the PH2 clock by four. The
prescaler gives the timer a resolution of 2.0 microseconds when a 4-MHz crystal is
used. The counter is incremented to increasing values during the low portion of the
PH2 clock cycle.
3
The double byte free-running counter can be read from either of two locations: the
timer registers (TMRH and TMRL) or the alternate counter registers (ACRH and
ACRL). Both locations will contain identical values. A read sequence containing
only a read of the LSB of the counter (TMRL/ACRL) will return the count value at
the time of the read. If a read of the counter accesses the MSB first (TMRH/ACRH),
it causes the LSB (TMRL/ACRL) to be transferred to a buffer. This buffer value
remains fixed after the first MSB byte read, even if the MSB is read several times.
The buffer is accessed when reading the counter LSB (TMRL/ACRL), and thus
completes a read sequence of the total counter value. When reading either the
timer or alternate counter registers, if the MSB is read, the LSB must also be read
to complete the read sequence. See Figure 10-2 and Figure 10-3.
4
5
6
7
8
9
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
TMRH7 TMRH6 TMRH5 TMRH4 TMRH3 TMRH2 TMRH1 TMRH0
TMRH
$0018
10
11
12
13
14
A
1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
TMRL7
TMRL6
TMRL5
TMRL4
TMRL3
TMRL2
TMRL1
TMRL0
TMRL
$0019
1
1
1
1
1
1
0
0
= Unimplemented
Figure 10-2. Timer Registers (TMRH/TMRL)
16
17
18
19
20
16-BIT TIMER
Rev. 1.0
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