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68HC805P18 参数 Datasheet PDF下载

68HC805P18图片预览
型号: 68HC805P18
PDF下载: 下载PDF文件 查看货源
内容描述: 规格(通用版) [SPECIFICATION (General Release)]
分类和应用:
文件页数/大小: 111 页 / 2802 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
GENERAL RELEASE SPECIFICATION  
Any enabled IRQ interrupt source sets the IRQ latch on the falling edge of the  
IRQ pin or a port A pin if port A interrupts have been enabled. If edge-only  
sensitivity is chosen by a mask option, only the IRQ latch output can activate a  
request to the CPU to generate the IRQ interrupt sequence. This makes the IRQ  
interrupt sensitive to the following cases:  
8
2
1.  
Falling edge on the IRQ pin with all enabled port A interrupt pins at a high  
level.  
3
2.  
Falling edge on any enabled port A interrupt pin with all other enabled  
port A interrupt pins and the IRQ pin at a high level.  
4
If level sensitivity is chosen, the active high state of the IRQ input can also  
activate an IRQ request to the CPU to generate the IRQ interrupt sequence.  
This makes the IRQ interrupt sensitive to the following cases:  
5
6
1.  
2.  
Low level on the IRQ pin  
7
Falling edge on the IRQ pin with all enabled port A interrupt pins at a high  
level  
8
3.  
4.  
Low level on any enabled port A interrupt pin  
Falling edge on any enabled port A interrupt pin with all enabled port A  
interrupt pins and the IRQ pin at a high level  
9
This interrupt is serviced by the interrupt service routine located at the address  
specified by the contents of $3FFA and $3FFB. The IRQ latch is automatically  
cleared by entering the interrupt service routine.  
10  
11  
12  
13  
14  
A
Optional External Interrupts (PA0–PA7)  
The IRQ interrupt can be triggered by the inputs on the PA0 through PA7 port  
pins if enabled by individual mask options. With pullup enabled, each port A pin  
can activate the IRQ interrupt function and the interrupt operation will be the  
same as for inputs to the IRQ pin. Once enabled by mask option, each individual  
port A pin can be disabled as an interrupt source if its corresponding DDR bit is  
configured for output mode.  
NOTE  
16  
17  
18  
19  
20  
The BIH and BIL instructions apply to the output of the logic OR  
function of the enabled PA0 through PA7 interrupt pins and the IRQ  
pin. The BIH and BIL instructions do not test only the state of the IRQ  
pin.  
INTERRUPTS  
Rev. 1.0  
For More Information On This Product,  
Go to: www.freescale.com  
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