Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
5.3 Internal Resets
The three internally generated resets are the initial power-on reset (POR), the COP
8
2
watchdog timer, and low-voltage reset (LVR) functions.
5.3.1 Power-On Reset (POR)
3
The internal POR is generated at power-up to allow the clock oscillator to stabilize.
The POR is strictly for power turn-on conditions and should not be used to detect
a drop in the power supply voltage. There is a 4064 PH2 clock cycle oscillator
stabilization delay after the oscillator becomes active.
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5
The POR will generate the RST signal and reset the MCU. The POR will also pull
the RESET pin low at the same time, allowing external devices to be reset with the
MCU. If any other reset function is active at the end of this 4064 PH2 clock cycle
delay, the RST signal will remain active until the other reset condition(s) end.
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7
5.3.2 Computer Operating Properly (COP) Reset
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When the COP watchdog timer is enabled (by MOR1, bit 0), the internal COP reset
is generated automatically by a timeout of the COP watchdog timer. This timer is
implemented with an 18-stage ripple counter that provides a time-out period of
65.5 ms when a 4-MHz oscillator is used. The COP watchdog counter is cleared
by writing a logical zero to bit zero at location $3FF0.
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10
11
12
13
14
A
The COP register is shared with the most significant bit (MSB) of an
unimplemented user interrupt vector as shown in Figure 5-2. Reading this location
will return the MSB of the unimplemented user interrupt vector. Writing to this
location will clear the COP watchdog timer.
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
$3FF0
R
COPR
—
—
—
—
—
—
R
—
—
16
17
18
19
20
= Unimplemented
= Reserved
Figure 5-2. Unimplemented Vector and
COP Watchdog Timer Register
RESETS
MC68HC805P18
5-2
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