Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
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2
SECTION 5
RESETS
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5.1 Introduction
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The MCU can be reset from four sources: one external input and three internal
reset conditions. The RESET pin is an input with a Schmitt trigger as shown in
Figure 5-1. The CPU and all peripheral modules will be reset by the RST signal
which is the logical OR of internal reset functions and is clocked by PH2.
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5.2 External Reset (RESET)
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The RESET input is the only external reset and is connected to an internal Schmitt
trigger. The external reset occurs whenever the RESET input is driven below the
lower threshold and remains in reset until the RESET pin rises above the upper
threshold. The upper and lower thresholds are given in SECTION 13
ELECTRICAL SPECIFICATIONS.
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A
TO IRQ
LOGIC
IRQ
D
LATCH
MODE
SELECT
RESET
R
(PULSE WIDTH =4 x E-CLK)
CLOCKED
ONE-SHOT
PH2
OSC
DATA
ADDRESS
COP WATCHDOG
(COPR)
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LOW-VOLTAGE
RESET (LVR)
CPU
RST
V
DD
S
D
POWER-ON RESET
(POR)
TO OTHER
PERIPHERALS
V
LATCH
DD
PH2
Figure 5-1. Reset Block Diagram
RESETS
Rev. 1.0
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