Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
NOTE
8
2
If enabled, the PA0 through PA7 pins will cause an IRQ interrupt only
if these individual pins are configured as inputs.
3
Input Capture Interrupt
4
The input capture interrupt is generated by the 16-bit timer as described in
SECTION 10 16-BIT TIMER. The input capture interrupt flag is located in
register TSR and its corresponding enable bit can be found in register TCR. The
I bit in the CCR must be clear in order for the input capture interrupt to be
enabled. The interrupt service routine address is specified by the contents of
memory locations $3FF8 and $3FF9.
5
6
7
Output Compare Interrupt
The output compare interrupt is generated by the 16-bit timer as described in
SECTION 10 16-BIT TIMER. The output compare interrupt flag is located in
register TSR and its corresponding enable bit can be found in register TCR. The
I bit in the CCR must be clear in order for the output compare interrupt to be
enabled. The interrupt service routine address is specified by the contents of
memory locations $3FF8 and $3FF9.
8
9
10
11
12
13
14
A
Timer Overflow Interrupt
The timer overflow interrupt is generated by the 16-bit timer as described in
SECTION 10 16-BIT TIMER. The timer overflow interrupt flag is located in
register TSR and its corresponding enable bit can be found in register TCR. The
I bit in the CCR must be clear in order for the timer overflow interrupt to be
enabled. This internal interrupt will vector to the interrupt service routine located
at the address specified by the contents of memory locations $3FF8 and $3FF9.
16
17
18
19
20
INTERRUPTS
MC68HC805P18
4-6
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