Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
5.3.3 Low-Voltage Reset (LVR)
If the LVR has been enabled via MOR1, the internal LVR reset is generated when
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the supply voltage to the V pin falls below a nominal 3.80 Vdc. The LVR
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threshold is not intended to be an accurate and stable trip point, but is intended to
ensure that the CPU will be held in reset when the V supply voltage is below
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reasonable operating limits. If the LVR is tripped for a short time, the LVR reset
signal will last at least two cycles of the CPU bus clock, PH2.
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The LVR will generate the RST signal which will reset the CPU and other
peripherals. Also, the LVR will establish the mode of operation based on the state
of the IRQ pin at the time the LVR signal ends. If any other reset function is active
at the end of the LVR reset signal, the RST signal will remain in the reset condition
until the other reset condition(s) end.
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NOTE
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The voltage of the IRQ pin must be between 0–V volts to stay in
the normal operation mode.
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A
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RESETS
Rev. 1.0
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