Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
FROM RESET
8
2
IS I BIT
SET?
Y
N
3
CLEAR IRQ
REQUEST
LATCH
IRQ
INTERRUPT?
Y
Y
4
N
TIMER
INTERRUPT?
5
N
STACK
PC, X, A, CC
6
SET
I BIT IN CCR
7
8
LOAD PC FROM:
SWI: $3FFC, $3FFD
IRQ: $3FFA-$3FFB
TIMER: $3FF8-$3FF9
9
10
11
12
13
14
A
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
Y
Y
N
RESTORE RESISTERS
FROM STACK
RTI
INSTRUCTION?
CC, A, X, PC
N
EXECUTE INSTRUCTION
16
17
18
19
20
Figure 4-1. Interrupt Processing Flowchart
External Interrupt (IRQ)
The IRQ pin drives an asynchronous interrupt to the CPU. An edge detector
flip-flop is latched on the falling edge of IRQ. If either the output from the internal
edge detector flip-flop or the level on the IRQ pin is low, a request is
synchronized to the CPU to generate the IRQ interrupt. If the edge-sensitive
only option is selected, the output of the internal edge detector flip-flop is
sampled and the input level on the IRQ pin is ignored. If port A interrupts are
INTERRUPTS
Rev. 1.0
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