Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
programmed as an option, a port A interrupt will use the same vector. The
interrupt service routine address is specified by the contents of memory
locations $3FFA and $3FFB.
8
2
NOTE
3
The internal interrupt latch is cleared 9 PH2 clock cycles after the
interrupt is recognized (after location $3FFA is read). Therefore,
another external interrupt pulse could be latched during the IRQ
service routine.
4
5
6
NOTE
7
When the edge- and level-sensitive option is selected, the voltage
applied to the IRQ pin must return to the high state before the RTI
instruction in the interrupt service routine is executed.
8
9
10
11
12
13
14
A
The IRQ pin is one source of an IRQ interrupt and a mask option can also enable
the port A pins (PA0 through PA7) to act as other IRQ interrupt sources. These
sources are all combined into a single ORing function to be latched by the IRQ
latch.
IRQ PIN
TO BIH & BIL
INSTRUCTION
SENSING
PA0
DDRA0
PA0 IRQ INHIBIT
(MASK OPTION)
V
DD
:
:
:
:
:
:
:
:
IRQ
LATCH
TO IRQ
PROCESSING
IN CPU
16
17
18
19
20
R
:
PA7
DDRA7
PA7 IRQ INHIBIT
(MASK OPTION)
RST
IRQ VECTOR FETCH
MASK OPTION
(IRQ LEVEL)
Figure 4-2. IRQ Function Block Diagram
INTERRUPTS
MC68HC805P18
4-4
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