Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
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SECTION 4
INTERRUPTS
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4.1 Introduction
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The MCU can be interrupted six different ways:
• Non-maskable software interrupt instruction (SWI)
• External asynchronous interrupt (IRQ)
• Input capture interrupt (TIMER)
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• Output compare interrupt (TIMER)
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• Timer overflow interrupt (TIMER)
• Port A interrupt (if selected via MOR2, bits 0 through 7).
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Interrupts cause the processor to save the register contents on the stack and to set
the interrupt mask (I bit) to prevent additional interrupts. Unlike reset, hardware
interrupts do not cause the current instruction execution to be halted, but are
considered pending until the current instruction is completed.
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A
When the current instruction is completed, the processor checks all pending
hardware interrupts. If interrupts are not masked (I bit in the condition code register
is clear) and the corresponding interrupt enable bit is set, the processor proceeds
with interrupt processing. Otherwise, the next instruction is fetched and executed.
The SWI is executed the same as any other instruction, regardless of the I bit state.
When an interrupt is to be processed, the CPU puts the register contents on the
stack, sets the I bit in the CCR, and fetches the address of the corresponding
interrupt service routine from the vector table at locations $3FF0 through $3FFF. If
more than one interrupt is pending when the interrupt vector is fetched, the
interrupt with the highest vector location shown in Table 4-1 will be serviced first.
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An RTI instruction is used to signify when the interrupt software service routine is
completed. The RTI instruction causes the CPU state to be recovered from the
stack and normal processing to resume at the next instruction that was to be
executed when the interrupt took place. Figure 4-1 shows the sequence of events
that occurs during interrupt processing.
INTERRUPTS
Rev. 1.0
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