Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
Table 4-1. Vector Addresses for Interrupts and Reset
8
2
Register
N/A
Flag Name
N/A
Interrupts
CPU Interrupt
RESET
SWI
Vector Address
$3FF3–$3FFF
$3FFC–$3FFD
$3FFA–$3FFB
$3FF8–$3FF9
$3FF8–$3FF9
$3FF8–$3FF9
$3FF6–$3FF7
$3FF4–$3FF5
$3FF2–$3FF3
$3FF0–$3FF1
Reset
N/A
N/A
Software
3
N/A
N/A
External Interrupt
Timer Input Capture
Timer Output Compare
Timer Overflow
Unimplemented
Unimplemented
Unimplemented
Unimplemented
IRQ
TSR
TSR
TSR
N/A
ICF
TIMER
TIMER
TIMER
N/A
4
OCF
TOF
N/A
5
6
N/A
N/A
N/A
N/A
N/A
N/A
7
N/A
N/A
N/A
8
4.2 Interrupt Types
9
The interrupts fall into three categories: reset, software, and hardware.
10
11
12
13
14
A
4.2.1 Reset Interrupt Sequence
The reset function is not in the strictest sense an interrupt; however, it is acted upon
in a similar manner as shown in Figure 4-1. A low level input on the RESET pin or
internally generated RST signal causes the program to vector to its starting
address which is specified by the contents of memory locations $3FFE and $3FFF.
The I bit in the condition code register is also set. The MCU is configured to a
known state during this type of reset as described in SECTION 5 RESETS.
4.2.2 Software Interrupt (SWI)
The SWI is an executable instruction. It is also a non-maskable interrupt since it is
executed regardless of the state of the I bit in the CCR. As with any instruction,
interrupts pending during the previous instruction will be serviced before the SWI
opcode is fetched. The interrupt service routine address for the SWI instruction is
specified by the contents of memory locations $3FFC and $3FFD.
16
17
18
19
20
4.2.3 Hardware Interrupts
All hardware interrupts are maskable by the I bit in the CCR. If the I bit is set, all
hardware interrupts (internal and external) are disabled. Clearing the I bit enables
the hardware interrupts. Four hardware interrupts are explained in the following
paragraphs.
INTERRUPTS
MC68HC805P18
4-2
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