Table 4-13 Quad Timer C Registers Address Map (Continued)
(TMRC_BASE = $00 F0C0)
Register Acronym
Address Offset
Register Description
Comparator Load Register 2
TMRC1_CMPLD2
TMRC1_COMSCR
$19
$1A
Comparator Status and Control Register
Reserved
TMRC2_CMP1
TMRC2_CMP2
TMRC2_CAP
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
Compare Register 1
Compare Register 2
Capture Register
TMRC2_LOAD
TMRC2_HOLD
TMRC2_CNTR
TMRC2_CTRL
TMRC2_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRC2_CMPLD1
TMRC2_CMPLD2
TMRC2_COMSCR
TMRC3_CMP1
TMRC3_CMP2
TMRC3_CAP
$30
$31
$32
$33
$34
$35
$36
$37
$38
$39
$3A
Compare Register 1
Compare Register 2
Capture Register
TMRC3_LOAD
TMRC3_HOLD
TMRC3_CNTR
TMRC3_CTRL
TMRC3_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
TMRC3_CMPLD1
TMRC3_CMPLD2
TMRC3_COMSCR
Table 4-14 Quad Timer D Registers Address Map
(TMRD_BASE = $00 F100)
Quad Timer D is NOT available in the 56F8167 device
Register Acronym
Address Offset
Register Description
Compare Register 1
TMRD0_CMP1
TMRD0_CMP2
TMRD0_CAP
$0
$1
$2
Compare Register 2
Capture Register
56F8367 Technical Data, Rev. 9
56
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
