Peripheral Memory Mapped Registers
Table 4-11 Quad Timer A Registers Address Map (Continued)
(TMRA_BASE = $00 F040)
Register Acronym
Address Offset
Register Description
Reserved
TMRA2_CMP1
TMRA2_CMP2
TMRA2_CAP
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
Compare Register 1
Compare Register 2
Capture Register
TMRA2_LOAD
TMRA2_HOLD
TMRA2_CNTR
TMRA2_CTRL
TMRA2_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRA2_CMPLD1
TMRA2_CMPLD2
TMRA2_COMSCR
TMRA3_CMP1
TMRA3_CMP2
TMRA3_CAP
$30
$31
$32
$33
$34
$35
$36
$37
$38
$39
$3A
Compare Register 1
Compare Register 2
Capture Register
TMRA3_LOAD
TMRA3_HOLD
TMRA3_CNTR
TMRA3_CTRL
TMRA3_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
TMRA3_CMPLD1
TMRA3_CMPLD2
TMRA3_COMSCR
Table 4-12 Quad Timer B Registers Address Map
(TMRB_BASE = $00 F080)
Quad Timer B is NOT available in the 56F8167 device
Register Acronym
Address Offset
Register Description
Compare Register 1
TMRB0_CMP1
TMRB0_CMP2
TMRB0_CAP
TMRB0_LOAD
TMRB0_HOLD
$0
$1
$2
$3
$4
Compare Register 2
Capture Register
Load Register
Hold Register
56F8367 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
53
FREESCALE [ Freescale ]
