Table 4-17 Quadrature Decoder 0 Registers Address Map (Continued)
(DEC0_BASE = $00 F180)
Register Acronym
Address Offset
Register Description
Revolution Counter Register
DEC0_REV
DEC0_REVH
DEC0_UPOS
DEC0_LPOS
DEC0_UPOSH
DEC0_LPOSH
DEC0_UIR
$5
$6
$7
$8
$9
$A
$B
$C
$D
Revolution Hold Register
Upper Position Counter Register
Lower Position Counter Register
Upper Position Hold Register
Lower Position Hold Register
Upper Initialization Register
Lower Initialization Register
Input Monitor Register
DEC0_LIR
DEC0_IMR
Table 4-18 Quadrature Decoder 1 Registers Address Map
(DEC1_BASE = $00 F190)
Quadrature Decoder 1 is NOT available in the 56F8167 device
Register Acronym
Address Offset
Register Description
Decoder Control Register
DEC1_DECCR
DEC1_FIR
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
$C
$D
Filter Interval Register
DEC1_WTR
DEC1_POSD
DEC1_POSDH
DEC1_REV
Watchdog Time-out Register
Position Difference Counter Register
Position Difference Counter Hold Register
Revolution Counter Register
Revolution Hold Register
DEC1_REVH
DEC1_UPOS
DEC1_LPOS
DEC1_UPOSH
DEC1_LPOSH
DEC1_UIR
Upper Position Counter Register
Lower Position Counter Register
Upper Position Hold Register
Lower Position Hold Register
Upper Initialization Register
Lower Initialization Register
Input Monitor Register
DEC1_LIR
DEC1_IMR
56F8367 Technical Data, Rev. 9
60
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
