Peripheral Memory Mapped Registers
Table 4-14 Quad Timer D Registers Address Map (Continued)
(TMRD_BASE = $00 F100)
Quad Timer D is NOT available in the 56F8167 device
Register Acronym
Address Offset
Register Description
TMRD0_LOAD
TMRD0_HOLD
TMRD0_CNTR
TMRD0_CTRL
TMRD0_SCR
$3
$4
$5
$6
$7
$8
$9
$A
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRD0_CMPLD1
TMRD0_CMPLD2
TMRD0_COMSCR
TMRD1_CMP1
TMRD1_CMP2
TMRD1_CAP
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
Compare Register 1
Compare Register 2
Capture Register
TMRD1_LOAD
TMRD1_HOLD
TMRD1_CNTR
TMRD1_CTRL
TMRD1_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRD1_CMPLD1
TMRD1_CMPLD2
TMRD1_COMSCR
TMRD2_CMP1
TMRD2_CMP2
TMRD2_CAP
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
Compare Register 1
Compare Register 2
Capture Register
TMRD2_LOAD
TMRD2_HOLD
TMRD2_CNTR
TMRD2_CTRL
TMRD2_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRD2_CMPLD1
TMRD2_CMPLD2
TMRD2_COMSCR
56F8367 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
57
FREESCALE [ Freescale ]
