Table 4-14 Quad Timer D Registers Address Map (Continued)
(TMRD_BASE = $00 F100)
Quad Timer D is NOT available in the 56F8167 device
Register Acronym
Address Offset
Register Description
Compare Register 1
TMRD3_CMP1
TMRD3_CMP2
TMRD3_CAP
$30
$31
$32
$33
$34
$35
$36
$37
$38
$39
$3A
Compare Register 2
Capture Register
TMRD3_LOAD
TMRD3_HOLD
TMRD3_CNTR
TMRD3_CTRL
TMRD3_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
TMRD3_CMPLD1
TMRD3_CMPLD2
TMRD3_COMSCR
Table 4-15 Pulse Width Modulator A Registers Address Map
(PWMA_BASE = $00 F140)
PWMA is NOT available in the 56F8167 device
Register Acronym
Address Offset
Register Description
PWMA_PMCTL
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
$C
$D
$E
$F
$10
Control Register
PWMA_PMFCTL
PWMA_PMFSA
Fault Control Register
Fault Status Acknowledge Register
Output Control Register
Counter Register
PWMA_PMOUT
PWMA_PMCNT
PWMA_PWMCM
PWMA_PWMVAL0
PWMA_PWMVAL1
PWMA_PWMVAL2
PWMA_PWMVAL3
PWMA_PWMVAL4
PWMA_PWMVAL5
PWMA_PMDEADTM
PWMA_PMDISMAP1
PWMA_PMDISMAP2
PWMA_PMCFG
Counter Modulo Register
Value Register 0
Value Register 1
Value Register 2
Value Register 3
Value Register 4
Value Register 5
Dead Time Register
Disable Mapping Register 1
Disable Mapping Register 2
Configure Register
PWMA_PMCCR
Channel Control Register
56F8367 Technical Data, Rev. 9
58
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
