Table 4-10 External Memory Integration Registers Address Map (Continued)
(EMI_BASE = $00 F020)
Register Acronym Address Offset
Register Description
Chip Select Timing Control Register 2
Chip Select Timing Control Register 3
Chip Select Timing Control Register 4
Chip Select Timing Control Register 5
Chip Select Timing Control Register 6
Chip Select Timing Control Register 7
Bus Control Register
Reset Value
CSTC 2
CSTC 3
CSTC 4
CSTC 5
CSTC 6
CSTC 7
BCR
$12
$13
$14
$15
$16
$17
$18
0x016B sets the default number of
wait states to 11 for both read and
write accesses
Table 4-11 Quad Timer A Registers Address Map
(TMRA_BASE = $00 F040)
Register Acronym
Address Offset
Register Description
Compare Register 1
TMRA0_CMP1
TMRA0_CMP2
TMRA0_CAP
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
Compare Register 2
Capture Register
TMRA0_LOAD
TMRA0_HOLD
TMRA0_CNTR
TMRA0_CTRL
TMRA0_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRA0_CMPLD1
TMRA0_CMPLD2
TMRA0_COMSCR
TMRA1_CMP1
TMRA1_CMP2
TMRA1_CAP
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
Compare Register 1
Compare Register 2
Capture Register
TMRA1_LOAD
TMRA1_HOLD
TMRA1_CNTR
TMRA1_CTRL
TMRA1_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
TMRA1_CMPLD1
TMRA1_CMPLD2
TMRA1_COMSCR
56F8367 Technical Data, Rev. 9
52
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
