Peripheral Memory Mapped Registers
Table 4-12 Quad Timer B Registers Address Map (Continued)
(TMRB_BASE = $00 F080)
Quad Timer B is NOT available in the 56F8167 device
Register Acronym
Address Offset
Register Description
TMRB3_LOAD
TMRB3_HOLD
TMRB3_CNTR
TMRB3_CTRL
TMRB3_SCR
$33
$34
$35
$36
$37
$38
$39
$3A
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
TMRB3_CMPLD1
TMRB3_CMPLD2
TMRB3_COMSCR
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Table 4-13 Quad Timer C Registers Address Map
(TMRC_BASE = $00 F0C0)
Register Acronym
Address Offset
Register Description
Compare Register 1
TMRC0_CMP1
TMRC0_CMP2
TMRC0_CAP
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
Compare Register 2
Capture Register
TMRC0_LOAD
TMRC0_HOLD
TMRC0_CNTR
TMRC0_CTRL
TMRC0_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRC0_CMPLD1
TMRC0_CMPLD2
TMRC0_COMSCR
TMRC1_CMP1
TMRC1_CMP2
TMRC1_CAP
$10
$11
$12
$13
$14
$15
$16
$17
$18
Compare Register 1
Compare Register 2
Capture Register
TMRC1_LOAD
TMRC1_HOLD
TMRC1_CNTR
TMRC1_CTRL
TMRC1_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
TMRC1_CMPLD1
56F8367 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
55
FREESCALE [ Freescale ]
