Peripheral Memory Mapped Registers
Table 4-9 Data Memory Peripheral Base Address Map Summary (Continued)
Peripheral
Power Supervisor
Prefix
Base Address
Table Number
LVI
FM
FC
X:$00 F360
X:$00 F400
X:$00 F800
X:$00 FA00
4-36
4-37
4-38
4-39
FM
FlexCAN
FlexCAN2
FC2
Table 4-10 External Memory Integration Registers Address Map
(EMI_BASE = $00 F020)
Register Acronym Address Offset
Register Description
Reset Value
Chip Select Base Address Register 0
0x0004 = 64K when EXTBOOT = 0 or
EMI_MODE = 0
CSBAR 0
$0
0x0008 = 1M when EMI_MODE = 1
(Selects entire program space for
SC0)
Chip Select Base Address Register 1
0x0004 = 64K when EMI_MODE = 0
0x0008 = 1M when EMI_MODE = 1
CSBAR 1
$1
(Selects A0 - 19 addressable data
space for CS1)
Chip Select Base Address Register 2
Chip Select Base Address Register 3
Chip Select Base Address Register 4
Chip Select Base Address Register 5
Chip Select Base Address Register 6
Chip Select Base Address Register 7
Chip Select Option Register 0
CSBAR 2
CSBAR 3
CSBAR 4
CSBAR 5
CSBAR 6
CSBAR 7
CSOR 0
$2
$3
$4
$5
$6
$7
$8
0x5FCB programmed for chip select
for program space, word wide, read
and write, 11 waits
Chip Select Option Register 1
0x5FAB programmed for chip select
for data space, word wide, read and
write, 11 waits
CSOR 1
$9
Chip Select Option Register 2
Chip Select Option Register 3
Chip Select Option Register 4
Chip Select Option Register 5
Chip Select Option Register 6
Chip Select Option Register 7
Chip Select Timing Control Register 0
Chip Select Timing Control Register 1
CSOR 2
CSOR 3
CSOR 4
CSOR 5
CSOR 6
CSOR 7
CSTC 0
CSTC 1
$A
$B
$C
$D
$E
$F
$10
$11
56F8367 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
51
FREESCALE [ Freescale ]
