Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued)
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
D7
28
K1
Input/
Output
In reset, Data Bus — D7 - D15 specify part of the data for external
output is program or data memory accesses.
disabled,
pull-up is Depending upon the state of the DRV bit in the EMI bus control
enabled
register (BCR), D7 - D15 are tri-stated when the external bus is
inactive.
Most designs will want to change the DRV state to DRV = 1 instead
of using the default setting.
(GPIOF0)
Input/
Port F GPIO — These nine GPIO pins can be individually
Output
programmed as input or output pins.
D8
(GPIOF1)
29
30
K3
K2
K4
A5
A4
B5
C4
A3
P5
At reset, these pins default to Data Bus functionality.
D9
(GPIOF2)
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOF_PUR register.
D10
(GPIOF3)
32
Example: GPIOF0, clear bit 0 in the GPIOF_PUR register.
D11
(GPIOF4)
149
150
151
152
153
52
D12
(GPIOF5)
D13
(GPIOF6)
D14
(GPIOF7)
D15
(GPIOF8)
RD
Output
In reset, Read Enable — RD is asserted during external memory read
output is cycles. When RD is asserted low, pins D0 - D15 become inputs
disabled, and an external device is enabled onto the data bus. When RD is
pull-up is deasserted high, the external data is latched inside the device.
enabled
When RD is asserted, it qualifies the A0 - A23, PS, DS, and CSn
pins. RD can be connected directly to the OE pin of a static RAM
or ROM.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), RD is tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead
of using the default setting.
To deactivate the internal pull-up resistor, set the CTRL bit in the
SIM_PUDR register.
56F8367 Technical Data, Rev. 9
24
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
