Signal Pins
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued)
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
A6
17
G1
Output
In reset, Address Bus — A6 - A7 specify two of the address lines for
output is external program or data memory accesses.
disabled,
pull-up is Depending upon the state of the DRV bit in the EMI bus control
enabled
register (BCR), A6 - A7 and EMI control signals are tri-stated when
the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead
of using the default setting.
(GPIOE2)
Schmitt
Input/
Output
Port E GPIO — These two GPIO pins can be individually
programmed as input or output pins.
A7
(GPIOE3)
18
19
G3
G2
After reset, the default state is Address Bus.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOE_PUR register.
Example: GPIOE2, clear bit 2 in the GPIOE_PUR register.
A8
Output
In reset, Address Bus— A8 - A15 specify eight of the address lines for
output is external program or data memory accesses.
disabled,
pull-up is Depending upon the state of the DRV bit in the EMI bus control
enabled
register (BCR), A8 - A15 and EMI control signals are tri-stated when
the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead
of using the default setting.
(GPIOA0)
Schmitt
Input/
Output
Port A GPIO — These eight GPIO pins can be individually
programmed as input or output pins.
A9
(GPIOA1)
20
21
22
23
24
25
26
H1
H2
H4
H3
J1
After reset, the default state is Address Bus.
A10
(GPIOA2)
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOA_PUR register.
A11
(GPIOA3)
Example: GPIOA0, clear bit 0 in the GPIOA_PUR register.
A12
(GPIOA4)
A13
(GPIOA5)
A14
(GPIOA6)
J2
A15
J3
(GPIOA7)
56F8367 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
21
FREESCALE [ Freescale ]
