Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued)
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
TXD1
49
P4
Output
In reset, Transmit Data — SCI1 transmit data output
output is
(GPIOD6)
Input/
Output
disabled, Port D GPIO — This GPIO pin can be individually programmed
pull-up is as an input or output pin.
enabled
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 6 in the
GPIOD_PUR register.
RXD1
50
N5
Input
Input,
pull-up
enabled
Receive Data — SCI1 receive data input
(GPIOD7)
Input/
Port D GPIO — This GPIO pin can be individually programmed
Output
as an input or output pin.
After reset, the default state is SCI input.
To deactivate the internal pull-up resistor, clear bit 7 in the
GPIOD_PUR register.
TCK
TMS
137
138
D8
A8
Schmitt
Input
Input,
Test Clock Input — This input pin provides a gated clock to
pulled low synchronize the test logic and shift serial data to the
internally JTAG/EOnCE port. The pin is connected internally to a pull-down
resistor.
Schmitt
Input
Input,
Test Mode Select Input — This input pin is used to sequence the
pulled high JTAG TAP controller’s state machine. It is sampled on the rising
internally edge of TCK and has an on-chip pull-up resistor.
To deactivate the internal pull-up resistor, set the JTAG bit in the
SIM_PUDR register.
Note: Always tie the TMS pin to VDD through a 2.2K resistor.
TDI
139
140
B8
D7
Schmitt
Input
Input,
Test Data Input — This input pin provides a serial input data
pulled high stream to the JTAG/EOnCE port. It is sampled on the rising edge
internally of TCK and has an on-chip pull-up resistor.
To deactivate the internal pull-up resistor, set the JTAG bit in the
SIM_PUDR register.
TDO
Output
In reset, Test Data Output — This tri-stateable output pin provides a serial
output is output data stream from the JTAG/EOnCE port. It is driven in the
disabled, shift-IR and shift-DR controller states, and changes on the falling
pull-up is edge of TCK.
enabled
56F8367 Technical Data, Rev. 9
28
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
