Signal Pins
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued)
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
GPIOD2
57
K6
Input/
Output
Input,
pull-up
enabled
Port D GPIO — These four GPIO pins can be individually
programmed as input or output pins.
(CS4)
Output
Chip Select — CS4 - CS7 may be programmed within the EMI
module to act as chip selects for specific areas of the external
memory map.
GPIOD3
(CS5)
58
59
60
N7
P7
L7
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), CS4 - CS7 are tri-stated when the external bus is
inactive.
GPIOD4
(CS6)
GPIOD5
(CS7)
Most designs will want to change the DRV state to DRV = 1 instead
of using the default setting.
At reset, these pins are configured as GPIO.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOD_PUR register.
Example: GPIOD2, clear bit 2 in the GPIOD_PUR register.
TXD0
4
B1
Output
In reset, Transmit Data — SCI0 transmit data output
output is
(GPIOE0)
Input/
Output
disabled, Port E GPIO — This GPIO pin can be individually programmed as
pull-up is an input or output pin.
enabled
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOE_PUR register.
RXD0
5
D2
Input
Input,
pull-up
enabled
Receive Data — SCI0 receive data input
(GPIOE1)
Input/
Port E GPIO — This GPIO pin can be individually programmed as
Output
an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 1 in the
GPIOE_PUR register.
56F8367 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
27
FREESCALE [ Freescale ]
