Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued)
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
XTAL
93
K12
Input/
Chip-driven Crystal Oscillator Output — This output connects the internal
Output
crystal oscillator output to an external crystal.
If an external clock is used, XTAL must be used as the input and
EXTAL connected to GND.
The input clock can be selected to provide the clock directly to the
core. This input clock can also be selected as the input clock for
the on-chip PLL.
CLKO
3
D3
Output
In reset, Clock Output — This pin outputs a buffered clock signal. Using
output is the SIM CLKO Select Register (SIM_CLKOSR), this pin can be
disabled programmed as any of the following: disabled, CLK_MSTR
(system clock), IPBus clock, oscillator output, prescaler clock and
postscaler clock. Other signals are also available for test
purposes.
See Part 6.5.7 for details.
A0
154
C3
Output
In reset, Address Bus — A0 - A5 specify six of the address lines for
output is external program or data memory accesses.
disabled,
pull-up is Depending upon the state of the DRV bit in the EMI bus control
enabled
register (BCR), A0 - A5 and EMI control signals are tri-stated when
the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead
of using the default setting.
(GPIOA8)
Input/
Port A GPIO — These six GPIO pins can be individually
Output
programmed as input or output pins.
A1
(GPIOA9)
10
11
12
13
14
E3
E4
F2
F1
F3
After reset, the default state is Address Bus.
A2
(GPIOA10)
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOA_PUR register.
A3
(GPIOA11)
Example: GPIOA8, clear bit 8 in the GPIOA_PUR register.
A4
(GPIOA12)
A5
(GPIOA13)
56F8367 Technical Data, Rev. 9
20
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
