Introduction
VDD_IO
VDDA_ADC
Power
Power
Quadrature
PHASEA0 (TA0, GPIOC4)
PHASEB0 (TA1, GPIOC5)
INDEX0 (TA2, GPIOC6)
HOME0 (TA3, GPIOC7)
7
1
1
1
1
1
Decoder 0
or Quad
Timer A or
GPIO
VDDA_OSC_PLL
Power
1
6
VSS
Ground
Ground
VSSA_ADC
1
1
56F8167
OCR_DIS
SCLK0
1
1
1
1
SPI0 or
GPIO
MOSI0 (GPIOE5)
MISO0 (GPIOE6)
SS0 (GPIOE7)
*VCAP1 - VCAP
4
Other
Supply
Ports
4
2
VPP1 & VPP
2
CLKMODE
EXTAL
XTAL
1
1
(SCLK1, GPIOC0)
(MOSI1, GPIOC1)
(MISO1, GPIOC2)
(SS1, GPIOC3)
PLL
and
Clock
1
1
1
1
SPI 1 or
GPIO
1
1
CLKO
A0 - A5 (GPIOA8 - 13)
A6 - A7 (GPIOE2 - 3)
A8 - A15 (GPIOA0 - 7)
6
2
(GPIOC8 - 10)
GPIO
3
External
Address
Bus
8
4
1
1
1
1
GPIOB0 - 3 (A16 - 19)
GPIOB4 (A20, prescaler_clock)
GPIOB5 (A21, SYS_CLK)
PWMB0 - 5
or GPIO
6
3
4
PWMB or
GPIO
ISB0 - 2 (GPIOD10 - 12)
FAULTB0 - 3
GPIOB6 (A22, SYS_CLK2)
GPIOB7 (A23, oscillator_clock)
ADCA
ADCB
ANA0 - 7
VREF
External
Data Bus
or GPIO
8
D0 - D6 (GPIOF9 - 15)
D7 - D15 (GPIOF0 - 8)
7
9
5
8
ANB0 - 7
RD
WR
1
1
1
1
6
External
Bus
Control or
GPIO
PS (CS0, GPIOD8)
DS (CS1, GPIOD9)
GPIOD0 - 5 (CS2 - 7)
TXD0 (GPIOE0)
RXD0 (GPIOE1)
SCI 0 or
GPIO
1
1
QUAD
TIMER C or
GPIO
TC0 - 1 (GPIOE8 - 9)
(GPIOE10 - 13)
2
4
TXD1 (GPIOD6)
RXD1 (GPIOD7)
SCI 1
or GPIO
1
1
IRQA
1
IRQB
1
1
TCK
TMS
TDI
1
EXTBOOT
EMI_MODE
INTERRUPT
/ PROGRAM
CONTROL
JTAG/
EOnCE
Port
1
1
1
RESET
RSTO
TDO
TRST
1
1
1
1
* When the on-chip regulator is disabled, these four pins become 2.5V VDD_CORE
.
1
Figure 2-2 56F8167 Signals Identified by Functional Group (160-pin LQFP)
1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality.
56F8367 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
17
FREESCALE [ Freescale ]
