VDD_IO
Power
Power
7
1
1
6
PHASEA0 (TA0, GPIOC4)
PHASEB0 (TA1, GPIOC5)
INDEX0 (TA2, GPIOC6)
HOME0 (TA3, GPIOC7)
VDDA_OSC_PLL
VDDA_ADC
Quadrature
Decoder 0
or Quad
1
1
1
1
Power
VSS
Ground
Ground
Timer A
VSSA_ADC
1
1
56F8367
OCR_DIS
SCLK0
1
1
1
1
SPI0 or
GPIO
MOSI0 (GPIOE5)
MISO0 (GPIOE6)
SS0 (GPIOE7)
*VCAP1 - VCAP
4
2
Other
Supply
Ports
4
VPP1 & VPP
2
CLKMODE
EXTAL
XTAL
1
1
Quadrature
Decoder 1 or
Quad Timer B
or SPI 1 or
GPIO
PHASEA1(TB0, SCLK1, GPIOC0)
PHASEB1 (TB1, MOSI1, GPIOC1)
INDEX1 (TB2, MISO1, GPIOC2)
HOME1 (TB3, SS1, GPIOC3)
PLL
and
Clock
1
1
1
1
1
1
CLKO
A0 - A5 (GPIOA8 - 13)
A6 - A7 (GPIOE2 - 3)
A8 - A15 (GPIOA0 - 7)
6
2
PWMA0 - 5
6
3
4
ISA0 - 2 (GPIOC8 - 10)
FAULTA0 - 3
PWMA
PWMB
External
Address
Bus
8
8
1
1
1
1
GPIOB0 - 7 (A16 - 23)
GPIOB4 (A20, prescaler_clock)
GPIOB5 (A21, SYS_CLK)
or GPIO
PWMB0 - 5
6
ISB0 - 2 (GPIOD10 - 12)
FAULTB0 - 3
GPIOB6 (A22, SYS_CLK2)
GPIOB7 (A23, oscillator_clock)
3
4
D0 - D6 (GPIOF9 - 15)
D7 - D15 (GPIOF0 - 8)
External
Data Bus
7
9
ANA0 - 7
VREF
8
ADCA
ADCB
5
8
ANB0 - 7
RD
1
1
WR
Temperature
Sense
Temp_Sense
PS/CS0 (GPIODF8)
DS/CS1 (GPIOFD9)
1
1
1
1
External
Bus
Control
CAN_RX
CAN_TX
GPIOD0 (CS2, CAN2_TX)
1
1
FlexCAN
GPIOD1 (CS3, CAN2_RX)
GPIOD2 - 5 (CS4 - 7)
1
4
Quad Timer
C and D or
GPIO
TC0 - 1 (GPIOE8 - 9)
2
4
TXD0 (GPIOE0)
RXD0 (GPIOE1)
SCI 0 or
GPIO
1
1
TD0 - 3 (GPIOE10 - 13)
TXD1 (GPIOD6)
RXD1 (GPIOD7)
SCI 1 or
GPIOD
1
1
IRQA
1
IRQB
1
1
TCK
TMS
TDI
EXTBOOT
EMI_MODE
INTERRUPT/
PROGRAM
CONTROL
1
JTAG/
EOnCE
Port
1
1
1
RESET
RSTO
TDO
TRST
1
1
1
1
* When the on-chip regulator is disabled, these four pins become 2.5V VDD_CORE
.
1
Figure 2-1 56F8367 Signals Identified by Functional Group (160-pin LQFP)
1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality.
56F8367 Technical Data, Rev. 9
16
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
