Table 4-19 GPIOD Registers Address Map
(GPIOD_BASE = $00 F180)
Register Acronym
Address Offset
Register Description
GPIOD_PUPEN
GPIOD_DATA
GPIOD_DDIR
GPIOD_PEREN
GPIOD_IASSRT
GPIOD_IEN
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
Pull-up Enable Register
Data Register
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Output Mode Control Register
Raw Data Input Register
GPIOD_IPOL
GPIOD_IPEND
GPIOD_IEDGE
GPIOD_PPOUTM
GPIOD_RDATA
GPIOD_DRIVE
Output Drive Strength Control Register
Table 4-20 Programmable Interval Timer 0 Registers Address Map
(PIT0_BASE = $00 F190)
Register Acronym
Address Offset
Register Description
PIT0_CTRL
PIT0_MOD
PIT0_CNTR
$0
$1
$2
Control Register
Modulo Register
Counter Register
Table 4-21 Programmable Interval Timer 1 Registers Address Map
(PIT1_BASE = $00 F1A0)
Register Acronym
Address Offset
Register Description
PIT1_CTRL
PIT1_MOD
PIT1_CNTR
$0
$1
$2
Control Register
Modulo Register
Counter Register
Table 4-22 Programmable Interval Timer 2 Registers Address Map
(PIT2_BASE = $00 F1B0)
Register Acronym
Address Offset
Register Description
PIT2_CTRL
PIT2_MOD
PIT2_CNTR
$0
$1
$2
Control Register
Modulo Register
Counter Register
56F8037 Data Sheet, Rev. 3
58
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
