Table 4-14 Clock Generation Module Registers Address Map
(OCCS_BASE = $00 F130)
Register Acronym
Address Offset
Register Description
OCCS_CTRL
OCCS_DIVBY
OCCS_STAT
$0
$1
$2
Control Register
Divide-By Register
Status Register
Reserved
OCCS_OCTRL
OCCS_CLKCHK
OCCS_PROT
$5
$6
$7
Oscillator Control Register
Clock Check Register
Protection Register
Table 4-15 Power Supervisor Registers Address Map
(PS_BASE = $00 F140)
Register Acronym
Address Offset
Register Description
PS_CTRL
PS_STAT
$0
$1
Control Register
Status Register
Reserved
Table 4-16 GPIOA Registers Address Map
(GPIOA_BASE = $00 F150)
Address Offset
Register Description
Register Acronym
GPIOA_PUPEN
GPIOA_DATA
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
Pull-up Enable Register
Data Register
GPIOA_DDIR
Data Direction Register
GPIOA_PEREN
GPIOA_IASSRT
GPIOA_IEN
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Output Mode Control Register
Raw Data Input Register
GPIOA_IPOL
GPIOA_IPEND
GPIOA_IEDGE
GPIOA_PPOUTM
GPIOA_RDATA
GPIOA_DRIVE
Output Drive Strength Control Register
56F8037 Data Sheet, Rev. 3
56
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
