Peripheral Memory-Mapped Registers
Table 4-12 SIM Registers Address Map
(SIM_BASE = $00 F100)
Register Acronym
Address Offset
Register Description
SIM_CTRL
SIM_RSTAT
SIM_SWC0
SIM_SWC1
SIM_SWC2
SIM_SWC3
SIM_MSHID
SIM_LSHID
SIM_PWR
$0
$1
$2
$3
$4
$5
$6
$7
$8
Control Register
Reset Status Register
Software Control Register 0
Software Control Register 1
Software Control Register 2
Software Control Register 3
Most Significant Half JTAG ID
Least Significant Half JTAG ID
Power Control Register
Reserved
SIM_CLKOUT
SIM_PCR
$A
$B
Clock Out Select Register
Peripheral Clock Rate Register
Peripheral Clock Enable Register 0
Peripheral Clock Enable Register 1
Peripheral STOP Disable Register 0
Peripheral STOP Disable Register 1
SIM_PCE0
SIM_PCE1
SIM_SD0
$C
$D
$E
SIM_SD1
$F
SIM_IOSAHI
SIM_IOSALO
SIM_PROT
SIM_GPSA0
SIM_GPSA1
SIM_GPSB0
SIM_GPSB1
SIM_GPSCD
SIM_IPS0
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
I/O Short Address Location High Register
I/O Short Address Location Low Register
Protection Register
GPIO Peripheral Select Register 0 for GPIOA
GPIO Peripheral Select Register 1 for GPIOA
GPIO Peripheral Select Register 0 for GPIOB
GPIO Peripheral Select Register 1 for GPIOB
GPIO Peripheral Select Register for GPIOC and GPIOD
Internal Peripheral Source Select Register 0 for PWM
Internal Peripheral Source Select Register 1 for DACs
Internal Peripheral Source Select Register 2 for TMRA
Reserved
SIM_IPS1
SIM_IPS2
Table 4-13 Computer Operating Properly Registers Address Map
(COP_BASE = $00 F120)
Register Acronym
Address Offset
Register Description
COP_CTRL
COP_TOUT
COP_CNTR
$0
$1
$2
Control Register
Time-Out Register
Counter Register
56F8037 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
55
FREESCALE [ Freescale ]
