Table 4-32 Flash Module Registers Address Map
(FM_BASE = $00 F400)
Register Acronym
Address Offset
Register Description
Clock Divider Register
FM_CLKDIV
FM_CNFG
$0
$1
Configuration Register
Reserved
$2
FM_SECHI
FM_SECLO
$3
Security High Half Register
Security Low Half Register
Reserved
$4
$5 - $9
$10
FM_PROT
Protection Register
Reserved
$11 - $12
$13
FM_USTAT
FM_CMD
User Status Register
Command Register
Reserved
$14
$15 - $17
$18
FM_DATA
FM_OPT1
FM_TSTSIG
Data Buffer Register
Reserved
$19 - $A
$1B
Information Option Register 1
Reserved
$1C
$1D
Test Array Signature Register
Table 4-33 MSCAN Registers Address Map
(MSCAN_BASE = $00 F800)
Register Acronym
Address Offset
Register Description
MSCAN_CTRL0
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0A
$0B
Control Register 0
MSCAN_CTRL1
MSCAN_BTR0
MSCAN_BTR1
MSCAN_RFLG
MSCAN_RIER
MSCAN_TFLG
MSCAN_TIER
MSCAN_TARQ
MSCAN_TAAK
MSCAN_TBSEL
MSCAN_IDAC
Control Register 1
Bus Timing Register 0
Bus Timing Register 1
Receiver Flag Register
Receiver Interrupt Enable Register
Transmitter Flag Register
Transmitter Interrupt Enable Register
Transmitter Message Abort Request Register
Transmitter Message Abort Acknowledge Register
Transmitter Buffer Selection Register
Identifier Acceptance Control Register
Reserved
MSCAN_MISC
$0D
$0E
Miscellaneous Register
MSCAN_RXERR
Receive Error Register
56F8037 Data Sheet, Rev. 3
62
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
