Table 4-10 Pulse Width Modulator Registers Address Map (Continued)
(PWM_BASE = $00 F0C0)
Register Acronym
Address Offset
Register Description
Disable Mapping Register 2
PWM_DMAP2
PWM_CNFG
PWM_CCTRL
PWM_PORT
PWM_ICCTRL
PWM_SCTRL
PWM_SYNC
PWM_FFILT0
PWM_FFILT1
PWM_FFILT2
PWM_FFILT3
$F
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
Configure Register
Channel Control Register
Port Register
Internal Correction Control Register
Source Control Register
Synchronization Window Register
Fault0 Filter Register
Fault1 Filter Register
Fault2 Filter Register
Fault3 Filter Register
Table 4-11 Interrupt Control Registers Address Map
(ITCN_BASE = $00 F0E0)
Register Acronym
Address Offset
Register Description
Interrupt Priority Register 0
ITCN_IPR0
ITCN_IPR1
ITCN_IPR2
ITCN_IPR3
ITCN_IPR4
ITCN_IPR5
ITCN_IPR6
ITCN_VBA
$0
$1
Interrupt Priority Register 1
Interrupt Priority Register 2
Interrupt Priority Register 3
Interrupt Priority Register 4
Interrupt Priority Register 5
Interrupt Priority Register 6
Vector Base Address Register
Fast Interrupt Match 0 Register
Fast Interrupt Vector Address Low 0 Register
Fast Interrupt Vector Address High 0 Register
Fast Interrupt Match 1 Register
Fast Interrupt Vector Address Low 1 Register
Fast Interrupt Vector Address High 1 Register
IRQ Pending Register 0
$2
$3
$4
$5
$6
$7
ITCN_FIM0
ITCN_FIVAL0
ITCN_FIVAH0
ITCN_FIM1
ITCN_FIVAL1
ITCN_FIVAH1
ITCN_IRQP0
ITCN_IRQP1
ITCN_IRQP2
ITCN_IRQP3
$8
$9
$A
$B
$C
$D
$E
$F
$10
$11
IRQ Pending Register 1
IRQ Pending Register 2
IRQ Pending Register 3
Reserved
ITCN_ICTRL
$16
Interrupt Control Register
Reserved
56F8037 Data Sheet, Rev. 3
54
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
