Peripheral Memory-Mapped Registers
Table 4-17 GPIOB Registers Address Map
(GPIOB_BASE = $00 F160)
Register Acronym
Address Offset
Register Description
GPIOB_PUPEN
GPIOB_DATA
GPIOB_DDIR
GPIOB_PEREN
GPIOB_IASSRT
GPIOB_IEN
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
Pull-up Enable Register
Data Register
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
GPIOB_IPOL
Interrupt Polarity Register
GPIOB_IPEND
GPIOB_IEDGE
GPIOB_PPOUTM
GPIOB_RDATA
GPIOB_DRIVE
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Output Mode Control Register
Raw Data Input Register
Output Drive Strength Control Register
Table 4-18 GPIOC Registers Address Map
(GPIOC_BASE = $00 F170)
Register Acronym
Address Offset
Register Description
GPIOC_PUPEN
GPIOC_DATA
GPIOC_DDIR
GPIOC_PEREN
GPIOC_IASSRT
GPIOC_IEN
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
Pull-up Enable Register
Data Register
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Output Mode Control Register
Raw Data Input Register
GPIOC_IPOL
GPIOC_IPEND
GPIOC_IEDGE
GPIOC_PPOUTM
GPIOC_RDATA
GPIOC_DRIVE
Output Drive Strength Control Register
56F8037 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
57
FREESCALE [ Freescale ]
