Table 4-27 Queued Serial Communication Interface 0 Registers Address Map
(QSCI0_BASE = $00 F200)
Register Acronym
Address Offset
Register Description
Baud Rate Register
QSCI0_RATE
QSCI0_CTRL1
QSCI0_CTRL2
QSCI0_STAT
QSCI0_DATA
$0
$1
$2
$3
$4
Control Register 1
Control Register 2
Status Register
Data Register
Table 4-28 Queued Serial Communication Interface 1 Registers Address Map
(QSCI1_BASE = $00 F210)
Register Acronym
Address Offset
Register Description
Baud Rate Register
QSCI1_RATE
QSCI1_CTRL1
QSCI1_CTRL2
QSCI1_STAT
QSCI1_DATA
$0
$1
$2
$3
$4
Control Register 1
Control Register 2
Status Register
Data Register
Table 4-29 Queued Serial Peripheral Interface 0 Registers Address Map
(QSPI0_BASE = $00 F220)
Register Acronym
Address Offset
Register Description
Status and Control Register
QSPI0_SCTRL
QSPI0_DSCTRL
QSPI0_DRCV
QSPI0_DXMIT
QSPI0_FIFO
$0
$1
$2
$3
$4
$5
Data Size and Control Register
Data Receive Register
Data Transmit Register
FIFO Control Register
Delay Register
QSPI0_DELAY
Table 4-30 Queued Serial Peripheral Interface 1 Registers Address Map
(QSPI1_BASE = $00 F230)
Register Acronym
Address Offset
Register Description
Status and Control Register
QSPI1_SCTRL
QSPI1_DSCTRL
QSPI1_DRCV
QSPI1_DXMIT
QSPI1_FIFO
$0
$1
$2
$3
$4
$5
Data Size and Control Register
Data Receive Register
Data Transmit Register
FIFO Control Register
Delay Register
QSPI1_DELAY
56F8037 Data Sheet, Rev. 3
60
Freescale Semiconductor
Preliminary