Peripheral Memory-Mapped Registers
Table 4-9 Analog-to-Digital Converter Registers Address Map (Continued)
(ADC_BASE = $00 F080)
Register Acronym
Address Offset
$24
Register Description
High Limit Register 0
ADC_HILIM0
ADC_HILIM1
ADC_HILIM2
ADC_HILIM3
ADC_HILIM4
ADC_HILIM5
ADC_HILIM6
ADC_HILIM7
ADC_OFFST0
ADC_OFFST1
ADC_OFFST2
ADC_OFFST3
ADC_OFFST4
ADC_OFFST5
ADC_OFFST6
ADC_OFFST7
ADC_PWR
$25
$26
$27
$28
$29
$2A
$2B
$2C
$2D
$2E
$2F
$30
$31
$32
$33
$34
$35
High Limit Register 1
High Limit Register 2
High Limit Register 3
High Limit Register 4
High Limit Register 5
High Limit Register 6
High Limit Register 7
Offset Register 0
Offset Register 1
Offset Register 2
Offset Register 3
Offset Register 4
Offset Register 5
Offset Register 6
Offset Register 7
Power Control Register
Calibration Register
Reserved
ADC_CAL
Table 4-10 Pulse Width Modulator Registers Address Map
(PWM_BASE = $00 F0C0)
Register Acronym
Address Offset
Register Description
PWM_CTRL
PWM_FCTRL
PWM_FLTACK
PWM_OUT
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
$C
$D
$E
Control Register
Fault Control Register
Fault Status Acknowledge Register
Output Control Register
Counter Register
PWM_CNTR
PWM_CMOD
PWM_VAL0
PWM_VAL1
PWM_VAL2
PWM_VAL3
PWM_VAL4
PWM_VAL5
PWM_DTIM0
PWM_DTIM1
PWM_DMAP1
Counter Modulo Register
Value Register 0
Value Register 1
Value Register 2
Value Register 3
Value Register 4
Value Register 5
Dead Time Register 0
Dead Time Register 1
Disable Mapping Register 1
56F8037 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
53
FREESCALE [ Freescale ]
