Table 4-9 Analog-to-Digital Converter Registers Address Map
(ADC_BASE = $00 F080)
Register Acronym
Address Offset
Register Description
Control Register 1
ADC_CTRL1
ADC_CTRL2
ADC_ZXCTRL
ADC_CLIST 1
ADC_CLIST 2
ADC_CLIST 3
ADC_CLIST 4
ADC_SDIS
$0
$1
Control Register 2
$2
Zero Crossing Control Register
Channel List Register 1
Channel List Register 2
Channel List Register 3
Channel List Register 4
Sample Disable Register
Status Register
$3
$4
$5
$6
$7
ADC_STAT
$8
ADC_RDY
$9
Conversion Ready Register
Limit Status Register
Zero Crossing Status Register
Result Register 0
ADC_LIMSTAT
ADC_ZXSTAT
ADC_RSLT0
ADC_RSLT1
ADC_RSLT2
ADC_RSLT3
ADC_RSLT4
ADC_RSLT5
ADC_RSLT6
ADC_RSLT7
ADC_RSLT8
ADC_RSLT9
ADC_RSLT10
ADC_RSLT11
ADC_RSLT12
ADC_RSLT13
ADC_RSLT14
ADC_RSLT15
ADC_LOLIM0
ADC_LOLIM1
ADC_LOLIM2
ADC_LOLIM3
ADC_LOLIM4
ADC_LOLIM5
ADC_LOLIM6
ADC_LOLIM7
$A
$B
$C
$D
Result Register 1
$E
Result Register 2
$F
Result Register 3
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
$1E
$1F
$20
$21
$22
$23
Result Register 4
Result Register 5
Result Register 6
Result Register 7
Result Register 8
Result Register 9
Result Register 10
Result Register 11
Result Register 12
Result Register 13
Result Register 14
Result Register 15
Low Limit Register 0
Low Limit Register 1
Low Limit Register 2
Low Limit Register 3
Low Limit Register 4
Low Limit Register 5
Low Limit Register 6
Low Limit Register 7
56F8037 Data Sheet, Rev. 3
52
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
