Peripheral Memory-Mapped Registers
Table 4-8 Quad Timer B Registers Address Map (Continued)
(TMRB_BASE = $00 F040)
Register Acronym
Address Offset
$12
Register Description
TMRB1_CAPT
TMRB1_LOAD
TMRB1_HOLD
TMRB1_CNTR
TMRB1_CTRL
TMRB1_SCTRL
TMRB1_CMPLD1
TMRB1_CMPLD2
TMRB1_CSCTRL
TMRB1_FILT
Capture Register
Load Register
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Input Filter Register
Reserved
TMRB2_COMP1
TMRB2_COMP2
TMRB2_CAPT
TMRB2_LOAD
TMRB2_HOLD
TMRB2_CNTR
TMRB2_CTRL
TMRB2_SCTRL
TMRB2_CMPLD1
TMRB2_CMPLD2
TMRB2_CSCTRL
TMRB2_FILT
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
$2B
Compare Register 1
Compare Register 2
Capture Register
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Input Filter Register
Reserved
TMRB3_COMP1
TMRB3_COMP2
TMRB3_CAPT
TMRB3_LOAD
TMRB3_HOLD
TMRB3_CNTR
TMRB3_CTRL
TMRB3_SCTRL
TMRB3_CMPLD1
TMRB3_CMPLD2
TMRB3_CSCTRL
TMRB3_FILT
$30
$31
$32
$33
$34
$35
$36
$37
$38
$39
$3A
$3B
Compare Register 1
Compare Register 2
Capture Register
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Input Filter Register
Reserved
56F8037 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
51