Table 4-7 Quad Timer A Registers Address Map (Continued)
(TMRA_BASE = $00 F000)
Register Acronym
Address Offset
Register Description
Comparator Load Register 2
TMRA2_CMPLD2
TMRA2_CSCTRL
TMRA2_FILT
$29
$2A
$2B
Comparator Status and Control Register
Input Filter Register
Reserved
TMRA3_COMP1
TMRA3_COMP2
TMRA3_CAPT
TMRA3_LOAD
TMRA3_HOLD
TMRA3_CNTR
TMRA3_CTRL
TMRA3_SCTRL
TMRA3_CMPLD1
TMRA3_CMPLD2
TMRA3_CSCTRL
TMRA3_FILT
$30
$31
$32
$33
$34
$35
$36
$37
$38
$39
$3A
$3B
Compare Register 1
Compare Register 2
Capture Register
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Input Filter Register
Reserved
Table 4-8 Quad Timer B Registers Address Map
(TMRB_BASE = $00 F040)
Register Acronym
Address Offset
Register Description
Compare Register 1
TMRB0_COMP1
TMRB0_COMP2
TMRB0_CAPT
TMRB0_LOAD
TMRB0_HOLD
TMRB0_CNTR
TMRB0_CTRL
TMRB0_SCTRL
TMRB0_CMPLD1
TMRB0_CMPLD2
TMRB0_CSCTRL
TMRB0_FILT
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
Compare Register 2
Capture Register
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Input Filter Register
Reserved
TMRB0_ENBL
TMRB1_COMP1
TMRB1_COMP2
$F
Timer Channel Enable Register
Compare Register 1
Compare Register 2
$10
$11
56F8037 Data Sheet, Rev. 3
50
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
